1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a transistor. More particularly, the invention relates to a method of manufacture capable of simultaneously forming a planar transistor and fin transistor using a simple process.
2. Description of Related Art
The transistor is the basic building block of contemporary semiconductor memory devices. Since transistors within a particular semiconductor device have many different operating requirements and characteristics, they are commonly implemented in different sizes and with very different structures.
For example, planar type transistors which generally have a well controlled threshold voltage are commonly used in respective cell regions of a semiconductor memory device. In contrast, fin type transistors which generally enjoy fast operating speed due to a relatively high operating current per unit area are commonly used in peripheral circuits surrounding a memory region, as well as the memory array region of a semiconductor memory device.
Conventionally, different transistors require separate fabrication sequences (i.e., application of a defined sequence of fabrication processes required to form a particular structure). Given the disparate transistor types used across the great range of circuits forming contemporary semiconductor devices, for example, this requirement for separate fabrication sequences has become increasingly unwieldy.
As semiconductor devices increase in integration density and computational complexity, different substrates or substrate portions are used to fabricate constituent components and elements. For example, a semiconductor memory device may be manufactured using a bulk silicon substrate, or a silicon-on-insulator (SOI) substrate. Generally speaking, SOI substrates have a structure wherein a single crystalline silicon layer is formed on a buried oxide (BOX) layer.
When a plurality of transistors is formed on a SOI substrate, individual transistors are isolated from one another by the buried oxide layer, such that “latch-up” between the adjacent transistors does not occur and overall parasitic capacitance is reduced. Additionally, since the channel region of each transistor is limited by the buried oxide layer, junction capacitance and junction current leakage between source/drain regions are reduced. Thus, the potential for short channel effects is reduced. Further, transistors formed on a SOI substrate generally operate at faster speeds using relatively less applied power, as compared with similar transistors formed on a bulk silicon substrate.
Unfortunately, the manufacturing costs associated with the use of a SOI substrate are markedly higher than costs associated with the use of a bulk silicon substrate, because the complexity of overall fabrication process used to form a semiconductor device on a SOI substrate is significantly greater. It would be highly desirable to form a semiconductor device having substantially the same performance characteristics on a bulk silicon substrate as on a SOI substrate. That is, without resort to the greater expense and complexity associated with a SOI substrate, it would be very desirable to form a transistor having reduced junction leakage current and junction capacitance, as well as a more competitive power operating point using mass production capabilities associated with bulk silicon substrates.